Real chips,
rebuilt small.

always_ff @(posedge clk or negedge rst_n) begin
  if (!rst_n) begin
    weight_reg <= '0;
    act_out    <= '0;
    psum_out   <= '0;
  end else begin
    if (load_weight)
      weight_reg <= weight_in;
    act_out  <= act_in;
    psum_out <= psum_in + ACC_W'(product);
  end
end

rtl/pe.sv, one multiply-accumulate cell of the array.

$ verilator --cc rtl/pe.sv rtl/systolic_array.sv \
    rtl/controller.sv rtl/tiny_tpu_top.sv \
    --top-module tiny_tpu_top -Wall

Verilated model written to wasm/obj_dir/

The same files, now C++ that any compiler can build.

$ em++ -O3 -std=c++17 bindings.cpp V*.cpp \
    verilated.cpp -lembind -s MODULARIZE=1 …

web/public/tiny_tpu.wasm   161 KB   (62 KB gzipped)

The whole chip, compiled to WebAssembly and shipped as one file.

Every number here is read from the compiled chip, not drawn by hand.